1. Field of the Invention
The present disclosure generally relates to the field of integrated circuits, and, more particularly, to a back end of line processing for a wire bonding structure in sophisticated metallization structures, including highly reactive metals, such as copper and the like.
2. Description of the Related Art
The manufacturing of integrated circuits involves many complex process steps to form circuit elements, such as transistors, capacitors, resistors and the like, in and above an appropriate semiconductor material. In recent years, enormous advances have been made in increasing integration density and overall functionality of the integrated circuits. These advances have been achieved by scaling the individual circuit elements to dimensions in the deep sub-micrometer range, with currently used critical dimensions, such as the gate length of a field effect transistor, of 30 nm and less. Hence, millions of circuit elements may be provided in a die, wherein a complex interconnect fabric may also have to be designed, in which each circuit element typically may be electrically connected to one or more other circuit elements. These interconnect structures are typically established in a metallization system comprising one or more wiring levels, in which appropriate metal features are formed according to the circuit configuration under consideration, in a similar manner as a multi-level printed circuit board, wherein, however, the dimensions of the metal features have to adapted to the dimensions of the semiconductor circuit elements, such as the transistors and the like. Over many decades, aluminum has been used as the metal of choice for forming the metal features in the metallization layers of the semiconductor devices, due to its moderately high thermal and electrical conductivity, its self-limiting creation of a passivating oxide layer and its compatibility with other materials and process techniques used for fabricating integrated devices. With the continuous reduction of the circuit dimensions, the dimensions of the metal features have resulted in a situation in which the overall signal delay in the devices is no longer restricted by the performance of the individual semiconductor circuit elements, such as the switching speed of the transistors, but is substantially determined by the parasitic time constants in the metallization system caused by the restricted conductivity of aluminum and the parasitic capacitance between neighboring metal regions. Therefore, in modern integrated circuits, highly conductive metals, such as copper and alloys thereof, are used to accommodate the high current densities encountered during the operation of the devices, while the parasitic capacitance may be reduced by using low-k dielectric materials, which are to be understood as dielectrics having a dielectric constant of 3.0 or less.
In an advanced stage of the manufacturing of integrated circuits, it is usually necessary to package a chip and provide leads and terminals for connecting the chip circuitry with the periphery. In some packaging techniques, chips, chip packages or other appropriate units may be connected by means of solder balls, formed from so-called solder bumps, that are formed on a corresponding layer of at least one of the units, for instance on a dielectric passivation layer of the microelectronic chip. In order to connect the microelectronic chip with the corresponding carrier, the surfaces of two respective units to be connected, i.e., the microelectronic chip comprising, for instance, a plurality of integrated circuits, and a corresponding package have formed thereon adequate pad arrangements to electrically connect the two units after reflowing the solder bumps provided at least on one of the units, for instance on the microelectronic chip. In other techniques, solder bumps may have to be formed that are to be connected to corresponding wires, or the solder bumps may be brought into contact with corresponding pad areas of another substrate acting as a heat sink. Consequently, it may be necessary to form a large number of solder bumps that may be distributed over the entire chip area, thereby providing, for example, the I/O (input/output) capability as well as the desired low capacitance arrangement required for high frequency applications of modern microelectronic chips that usually include complex circuitry, such as microprocessors, storage circuits and the like, and/or include a plurality of integrated circuits forming a complete complex circuit system.
Another approach for connecting chips with a package includes wire bonding techniques, which have been successfully developed over the last decades on the basis of aluminum and are still well established and represent the dominant technology for connecting the fast majority of semiconductor chips to a carrier substrate, wherein aluminum-based bond pads are usually provided which are contacted by an appropriate wire made of aluminum, copper, gold and the like. During the wire bonding process, the bond wire is treated to form a small ball at one end that is then brought into contact with the bond pad. Upon applying pressure, elevated temperature and ultrasonic energy, the wire ball is welded to the bond pad to form an intermetallic connection. However, many advanced semiconductor devices may have a copper-based metallization structure in view of device performance, integration density and process compatibility in facilities fabricating a wide variety of different products, wherein the connection to the carrier substrate is established by wire bonding, due to less demanding I/O capabilities as compared to, for instance, CPUs and other highly complex ICs, and the economic advantages of the wire bonding techniques over complex bump-based techniques. In a production environment, however, the wire bonding on copper bond pads is very difficult to achieve due to an inhomogeneous self-oxidization of the copper surface in combination with extensive corrosion, which may result in highly non-reliable bond connections. For this reason, a different terminal metal, such as an aluminum metal layer, may be used in an advanced metallization structure based on copper, possibly in combination with low-k dielectrics, which may result in a more complex manufacturing process, since respective process tools and processes for forming and patterning aluminum layers have to be provided in the production line. For example, for modern CPUs, in which both wire bonding and direct solder contact regimes using bump structures are to be employed, for instance for packaging respective test structures for monitoring the overall complex process flow of CPUs, significant additional efforts may have to be made during the formation of the bump structure for actual die regions including the CPUs and the wire bonding pads for respective test structures, as will be described in more detail with reference to FIGS. 1a-1c. 
FIG. 1a schematically illustrates a cross-sectional view of a conventional semiconductor device 100 in an advanced manufacturing stage. The semiconductor device 100 comprises a substrate 101, which may have formed therein circuit elements and other microstructural elements that, for convenience, are not shown in FIG. 1 a. The device 100 comprises one or more metallization layers including copper-based metal lines and vias, wherein, for convenience, the very last metallization layer 110 is shown, which may comprise a dielectric material 111 having formed therein a copper-containing metal region 112. That is, the metal region 112 may be formed of copper or a copper alloy, possibly in combination with respective barrier materials (not shown), so as to suppress any interaction between the dielectric material 111 and the copper material in the region 112. The metal region 112 may be electrically connected to any circuit elements representing an integrated circuit in accordance with a specific circuit arrangement, or the metal region 112 may represent a contact area connecting to device features representing a test structure so as to characterize specific device characteristics, such as electromigration performance, reliability of gate dielectrics and the like. The semiconductor device 100 further comprises a passivation layer stack 120, which may comprise a plurality of individual layers, indicated as dielectric layers 121, 122 and 123. For example, the dielectric layer 121 may be in direct contact with the metal region 112 and may be comprised of any appropriate material so as to act a as a cap layer for confining the copper material in the region 112. For example, the dielectric layer 121 may be comprised of silicon nitride, silicon carbide, nitrogen-containing silicon carbide and the like. Moreover, the layers 122 and 123 may be provided in any appropriate material composition so as to comply with the further processing of the device 100 and act as an appropriate passivation layer to insure integrity of any underlying components. For example, silicon dioxide, silicon oxynitride, silicon nitride and the like may be used for the dielectric layer 122, and also for the layer 123, depending on the overall process and device requirements. As shown, the passivation layer 120 may expose an appropriate portion of the metal region 112 as may be required for providing an appropriate bond area for receiving a bond wire 130. However, due to the highly reactive nature of the exposed surface portion of the metal region 112, corresponding surface contaminants, such as corrosive areas and the like 112A, may have been created in a more or less pronounced manner, depending on the process history of the device 100.
The semiconductor device 100 as shown in FIG. 1a may be formed on the basis of the following processes. Initially, the substrate 101 and any circuit elements contained therein may be manufactured on the basis of well-established process techniques, wherein, in sophisticated applications, circuit elements having critical dimensions on the order of magnitude of approximately 50 nm and less may be formed, followed by application of the one or more metallization layers 110 including copper-based metal lines and vias, wherein typically low-k dielectric materials are used for at least some of the dielectric materials in the metallization system of the device 100. The process sequence for forming the metallization layer 110 representing the very last metallization level of the device 100 typically includes the deposition of the dielectric material 111 and the patterning thereof, followed by filling in the copper-containing material, for instance on the basis of electrochemical deposition techniques, wherein the deposition of appropriate barrier materials, such as tantalum, tantalum nitride and the like, may precede the deposition of the copper material. After removal of any excess material, the dielectric layer 121 may be formed, for instance, by appropriate deposition techniques, thereby confining the copper-based materials, such as the metal region 112. Next, the further dielectric layers 122 and 123 of the passivation layer stack 120 may be formed on the layer 121 on the basis of any appropriate deposition technique, such as plasma enhanced chemical vapor deposition (PECVD) and the like. Thereafter, a photolithography process is performed to provide a resist mask (not shown) having a shape and dimension that substantially determines the actual bond area for connecting the bond wire 130 with the exposed portion of the metal region 112. Subsequently, the dielectric layer stack 120 may be patterned on the basis of the previously defined resist mask, which may finally be removed by well-established process techniques. As previously explained, a copper-containing surface that may be exposed during various manufacturing stages may readily react with aggressive components, such as oxygen, fluorine and the like, thereby creating the contaminants 112A in a highly non-homogeneous manner and providing very non-uniform process conditions during a bond process for connecting the bond wire 130 with the metal region 112. Consequently, the reliable intermetallic connection between the bond wire 130 and the surface of the metal region 112 may be difficult to be achieved and, therefore, in conventional approaches, the device 100 may receive an aluminum-based terminal metal layer so as to allow the application of well-approved wire bonding techniques on the basis of aluminum.
FIG. 1b schematically illustrates the conventional semiconductor device 100 in a further advanced manufacturing stage, in which an aluminum layer 131 may be formed above the exposed portion of the metal region 112. Furthermore, as shown, a barrier/adhesion layer 132 may be positioned between the aluminum layer 131 and the metal region 112 and the respective part of the dielectric layer stack 120. The barrier/adhesion layer 132 may, for instance, be comprised of tantalum, tantalum nitride, titanium, titanium nitride or other similar metals and compounds thereof as are typically used in combination with copper metallization systems in order to effectively reduce copper diffusion and enhance adhesion of the aluminum layer 131. Typically, the device 100 as shown in FIG. 1b may be formed by first depositing the barrier/adhesion layer 132, for instance on the basis of sputter deposition techniques, followed by the deposition of the aluminum layer 131, for instance by sputter deposition, chemical vapor deposition and the like. Next, a lithography process is performed to create a resist mask (not shown), which may be used as an etch mask during a reactive etch process, which may be performed, for instance, on the basis of a complex chlorine-based etch chemistry in order to obtain the patterned aluminum layer 131, as shown in FIG. 1b. Furthermore, the respective etch process may also include a separate etch step for etching through the barrier/adhesion layer 132, followed by a wet chemical process for removing any corrosive etch residues generated during the complex aluminum etch step.
FIG. 1c schematically illustrates the semiconductor device 100 in a further advanced manufacturing stage, in which the bond wire 130 may be bonded to the aluminum layer 131 by well-established process techniques, in which an end of the bond wire 130 may be attached to the exposed surface of the aluminum layer 131 while also applying heat and/or ultrasonic energy and pressure, thereby obtaining an intermetallic connection between a portion of the aluminum layer 131 and the bond wire 130.
Consequently, in the conventional approach described above, efficient wire bond techniques may be used on the basis of the aluminum layer 131, thereby, however, requiring a complex process sequence for depositing and patterning the barrier/adhesion layer 132 and the aluminum layer 131. Consequently, in a complex manufacturing environment, respective resources for depositing and patterning the aluminum layer 131 in combination with the barrier/adhesion layer 132 may have to be provided in addition to equipment and materials required for the formation of a complex copper-based metallization system, thereby contributing to increased cycle times and thus production costs.
The present disclosure is directed to various methods and devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.